AMD began mixing nodes in 2019 when it used the 7 nm node for the Zen 2 microarchitecture's core complex die (CCD) and the 12 nm node for the IO die. AMD recently confirmed to Tom's Hardware that Zen 4 will use three nodes: 5 nm for the CCD, 6 nm for the IO die, and 7 nm for the V-Cache.
During its recent ISSCC presentation, AMD discussed some of the challenges it faced when stacking one node on top of another. To allow them to be connected, both the 7950X3D and the original 5800X3D have their V-Caches positioned over their regular L3 caches. The configuration also keeps the V-Cache away from the heat generated by the cores. While the V-Cache neatly fits over the L3 cache in the 5800X3D, it overlaps with the L2 caches on the core edges in the 7950X3D.
Part of the issue stemmed from AMD's decision to double the amount of L2 cache in each core from 0.5 MB in Zen 3 to 1 MB in Zen 4. However, it circumvented the additional space constraints by drilling holes through the L2 caches for the through-silicon vias (TSVs) that deliver power to the V-Cache. The signal TSVs are still generated by the controller in the center of the CCD, but AMD has optimized them to reduce their footprint by 50%.
AMD reduced the size of the V-Cache from 41 mm2 to 36 mm2 while keeping the same 4.7 B transistors. TSMC manufactures the cache on a new 7 nm node developed specifically for SRAM. As a result, despite the CCD being manufactured on the much smaller 5 nm node, the V-Cache has 32% more transistors per square millimeter.
All of AMD's improvements and workarounds result in a 25% increase in bandwidth to 2.5 TB/s and an unspecified increase in efficiency. Not bad for nine months of development time between the first and second generations of a supplemental chiplet. Hopefully, it will prove its worth when the Ryzen 7 7800X3D arrives in a month.