Leaked Slides Reference AMD Zen 5 Microarchitecture

It is said that the next-generation "Zen 5" microarchitecture was talked about in a couple of slides that were leaked from AMD's private presentation. Inside the company, the "Zen 5" core with better performance is called "Nirvana," and the CPU core die built on "Nirvana" cores is codenamed "Eldora." The company will use these CCDs to make either Ryzen "Granite Ridge" PC processors or EPYC "Turin" server processors. Next-generation mobile CPUs from the company could also use these cores as part of heterogeneous CCXs (CPU core complexes), along with "Zen 5c" low-power cores.

Broadly speaking, AMD says that "Zen 5" will have a 10% to 15% higher IPC than "Zen 4." The core will have a 48 KB L1D cache instead of the 32 KB one it has now. When it comes to the core itself, it has an 8-wide dispatch from the micro-op queue instead of 6-wide dispatch in "Zen 4." The integer execution step will have 6 ALUs instead of 4. It is possible for the floating point unit to work with FP-512. AMD has raised the highest number of cores per CCX from 8 to 16, which is probably the most important news. At this point, we don't know if it means that the "Eldora" CCD will have 16 cores or that the "Zen 5c" cloud-specific CCD will have 16 cores in a single CCX instead of two CCXs with smaller L3 caches. When AMD makes "Eldora," they use the TSMC 4 nm EUV node. The mobile processor built on "Zen 5" might use the more advanced TSMC 3 nm EUV node.

AMD also uses an interesting way to talk about its CPU core designs on the first slide. This means that "Zen 3" and "Zen 5" are new cores and "Zen 4" and the upcoming "Zen 6" are leveraged cores. If you remember, "Zen 3" gave a huge 19% IPC boost over "Zen 2," which helped AMD take over the CPU market. Even though the "Zen 5" core is only expected to improve IPC by 15% over "Zen 4," it is still expected to have a big effect on AMD's ability to compete.

AMD is looking forward to a 10% rise in instruction per cycle (IPC) over "Zen 5," new FP16 features for the core, and a 32-core CCX (maximum core count) for the "Zen 6" microarchitecture and "Morpheus" core. This would lead to a second round of big growth in the number of CPU cores.

We can see that AMD added an even more advanced branch prediction unit to the "Zen 5" core when we look more closely. Don't forget that changes to branch predictors were the main reason for the generational IPC gain of "Zen 4." The new branch predictor can do zero bubble conditional branches, is more accurate, and has a bigger BTB (branch target buffer). We already said that the core has a bigger 48-KB L1D cache and an unknown bigger D-TLB. There is more speed in the front-end and load/store stages thanks to dual basic block fetch units, 8-wide op dispatch/rename; Op Fusion, a 50% rise in ALCs, a wider execution window, a better prefetcher, and changes to the CPU core ISA and security. The L2 cache that is set aside for each core stays at 1 MB.